Epson Doubles Productivity in LCD Controller Chip Tapeout with Encounter RTL Compiler; Cadence Global Synthesis Significantly Slashes Design Turnaround Time and Synthesis Runtime
SAN JOSE, Calif.—(BUSINESS WIRE)—July 12, 2005—
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN)
today announced that Seiko Epson Corporation ("Epson") of Japan
doubled productivity in the production tapeout of a high-volume LCD
controller chip using Cadence(R) Encounter(TM) RTL Compiler synthesis.
A 50 percent reduction in synthesis runtime, top-down synthesis and a
clean netlist with the ability to route with no detours all
contributed to timing closure and a substantial improvement in time to
market for Epson.
Encounter RTL Compiler, part of the Encounter digital IC design
platform, shortens design turnaround time by delivering superior
quality of silicon (QoS) through physical design. In addition to fast
runtimes, Encounter RTL Compiler offers a true top-down synthesis
methodology to avoid the lengthy manual effort of block-level
integration.
Epson is a global leader in electronics devices including
semiconductors and LCD displays, as well as imaging products including
printers and projectors.
"LCD Controllers are one of the most important products for
Epson's semiconductor business, and design turnaround time is the most
critical factor in maintaining our leadership position in this highly
competitive market," said Kanji Aoki, manager of the IC Design
Technology Department at Epson. "With its leading-edge technology,
Encounter RTL Compiler helped us meet the design schedule. Our
designers will continue to follow the top-down synthesis method
enabled by Encounter RTL Compiler to maximize our time-to-market
advantages."
Interconnect-related parameters in nanometer designs require a new
metric for synthesis results that includes performance, area, and
power measured with wires. Cadence defines this as quality of silicon.
Cadence Encounter RTL Compiler's global synthesis enables designers to
achieve the highest QoS in less time and with less effort.
"We are excited that Encounter RTL Compiler played a significant
role in enabling Epson to meet its design goals and successfully tape
out a key high-volume production chip," said Dr. Chi-Ping Hsu,
corporate vice president at Cadence. "This is another proof point of
how Encounter RTL Compiler enables customers like Epson to design
smaller and faster chips more economically and in less time."
About Cadence
Cadence enables global electronic-design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software and hardware,
methodologies, and services to design and verify advanced
semiconductors, consumer electronics, networking and
telecommunications equipment, and computer systems. Cadence reported
2004 revenues of approximately $1.2 billion, and has approximately
4,700 employees. The company is headquartered in San Jose, Calif.,
with sales offices, design centers, and research facilities around the
world to serve the global electronics industry. More information about
the company, its products, and services is available at
www.cadence.com.
Cadence and the Cadence logo are registered trademarks, and
Encounter is a trademark of Cadence Design Systems, Inc. All other
trademarks are the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Michael Fournell, 408-428-5135
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